Voltage Swing On Bitline evaluator uses Voltage Swing on Bitline = (Positive Voltage/2)*Cell Capacitance/(Cell Capacitance+Bit Capacitance) to evaluate the Voltage Swing on Bitline, The Voltage Swing On Bitline formula is defined as Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation. ... The proposed SRAM that stores four bits in one block can achieve a minimum voltage of 0.42 V and a read delay that is 62.6 times lesser than that of the average-8T SRAM based on the 22-nm FinFET technology. Voltage Swing on Bitline is denoted by ΔV symbol.
How to evaluate Voltage Swing On Bitline using this online evaluator? To use this online evaluator for Voltage Swing On Bitline, enter Positive Voltage (Vdd), Cell Capacitance (Ccell) & Bit Capacitance (Cbit) and hit the calculate button.