Output Clock Phase evaluator uses Output Clock Phase = 2*pi*VCO Control Voltage*VCO Gain to evaluate the Output Clock Phase, The Output Clock Phase formula is defined as the amount of time it takes from the clock at the pin of the FPGA, to the output signal at the FPGA. Output Clock Phase is denoted by Φout symbol.
How to evaluate Output Clock Phase using this online evaluator? To use this online evaluator for Output Clock Phase, enter VCO Control Voltage (Vctrl) & VCO Gain (Kvco) and hit the calculate button.